Within a digital and/or an analog system, a single event can cause one or more voltage pulses to propagate through the system. The phrase “single event” typically refers to a collision of an energetic particle, a cosmic ray, e.g., a proton, or the like, with an integrated circuit device (IC) of the system. A pulse generated in consequence of the single event is referred to as a “single event transient” or “SET.”
While propagation of an SET through a system is not desirable, an SET is not a change in state of some part of the system, as is a “single event upset” or “SEU.” In this respect, an SET can be distinguished from an SEU. An SEU generally refers to a change of state of a memory cell, e.g., a change from zero to one or a change from one to zero, caused by an SET. SEUs can manifest themselves within digital, analog, and optical components of a system or may have effects in surrounding interface circuitry. Thus, when an SET results in an incorrect value being latched into a sequential logic unit, for example, the SET is considered an SEU.
SEUs are generally referred to as “soft” errors in that a reset or rewriting of the IC typically causes normal device behavior after the occurrence of the SEU. In general, any “soft” malfunction of a bit that causes infrequent errors relative to the rate at which such errors are fixed by mitigation techniques and which has a relatively low correlation between errors can be considered an SEU.
One way of mitigating the effects of SETs is through the application of a technique called Triple Module Redundancy (TMR). TMR refers to the triplication of particular portions of a circuit design. For example, selected modules and data signals can be triplicated. At various points within the circuit, voter circuits can be inserted to determine which of the triplicated data signals is the correct or accurate data signal.
While TMR works well with respect to the internal circuitry of an IC, TMR can be impractical to implement for input/output (I/O) pins of an IC. Some ICs, for example, have thousands of I/O pins, making triplication very costly. TMR, as applied to I/O pins, also adds to the complexity of the IC. Further, not all devices that are to be coupled to an IC that utilizes TMR provide triplicated I/O pins. Triplicated I/O pins also add to the size, complexity, and therefore, cost of the printed circuit (PC) board upon which an IC with triplicated I/O pins is disposed.